The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2025
Filed:
Mar. 29, 2024
Intel Corporation, Santa Clara, CA (US);
Stephen Palermo, Chandler, AZ (US);
Bradley Chaddick, Portland, OR (US);
Gage Eads, Austin, TX (US);
Mrittika Ganguli, Tempe, AZ (US);
Abhishek Khade, Chandler, AZ (US);
Abhirupa Layek, Chandler, AZ (US);
Sarita Maini, Tempe, AZ (US);
Niall Mcdonnell, Limerick, IE;
Rahul Shah, Chandler, AZ (US);
Shrikant Shah, Chandler, AZ (US);
William Burroughs, Macungie, PA (US);
David Sonnier, Austin, TX (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.