The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

May. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ching-Jung Yang, Pingzhen, TW;

Yen-Ping Wang, Hemei Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/11003 (2013.01); H01L 2224/1111 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/1184 (2013.01); H01L 2224/1191 (2013.01); H01L 2224/13015 (2013.01); H01L 2224/13019 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14051 (2013.01); H01L 2224/14179 (2013.01); H01L 2224/81141 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81815 (2013.01);
Abstract

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.


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