The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Jun. 23, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bernd Waidhas, Pettendorf, DE;

Carlton Hanna, Santa Clara, CA (US);

Stephen Morein, San Jose, CA (US);

Lizabeth Keser, San Diego, CA (US);

Georg Seidemann, Landshut, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/36 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 23/36 (2013.01); H01L 23/50 (2013.01); H01L 23/5222 (2013.01); H01L 23/5227 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H05K 1/0262 (2013.01); H05K 1/0254 (2013.01); H05K 2201/09609 (2013.01);
Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.


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