The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

May. 03, 2022
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventor:

Darrell Glenn Hill, Chandler, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/76 (2006.01); H01L 21/765 (2006.01); H01L 23/48 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/118 (2025.01); H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 21/31116 (2013.01); H01L 21/7605 (2013.01); H01L 21/765 (2013.01); H01L 23/481 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01); H10D 64/111 (2025.01);
Abstract

A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel opening, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel opening, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel opening prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel opening, the length of the gate structure can be advantageously decreased.


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