The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2025
Filed:
Dec. 27, 2023
Applicant:
Adeia Semiconductor Solutions Llc, San Jose, CA (US);
Inventors:
Kangguo Cheng, Schenectady, NY (US);
Juntao Li, Cohoes, NY (US);
Heng Wu, Guilderland, NY (US);
Peng Xu, Guilderland, NY (US);
Assignee:
Adeia Semiconductor Solutions LLC, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/00 (2025.01); B82Y 10/00 (2011.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/021 (2025.01); B82Y 10/00 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/31116 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H10D 30/0243 (2025.01); H10D 30/43 (2025.01); H10D 30/6212 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01);
Abstract
Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.