The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Jul. 28, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tetsuji Ueno, Hsinchu, TW;

Ming-Hua Yu, Hsinchu, TW;

Chan-Lon Yang, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C23C 16/02 (2006.01); C23C 16/44 (2006.01); C30B 25/18 (2006.01); C30B 29/06 (2006.01); H10D 30/01 (2025.01); H10D 62/834 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 62/834 (2025.01); C23C 16/0218 (2013.01); C23C 16/4408 (2013.01); C30B 25/186 (2013.01); C30B 29/06 (2013.01); H01L 21/02532 (2013.01); H01L 21/0262 (2013.01); H01L 21/02661 (2013.01); H10D 30/024 (2025.01); H10D 30/0323 (2025.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H10D 30/027 (2025.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 30/797 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.


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