The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2025
Filed:
Sep. 23, 2022
Changxin Memory Technologies, Inc., Hefei, CN;
Semyeong Jang, Hefei, CN;
Joonsuk Moon, Hefei, CN;
Deyuan Xiao, Hefei, CN;
Minki Hong, Hefei, CN;
Jo-Lan Chin, Hefei, CN;
Kyongtaek Lee, Hefei, CN;
CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei, CN;
Abstract
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, where the base is provided with an array region and a peripheral region, the array region is provided with vertical transistor structures, the vertical transistor structures are arranged in an array in the array region, and the peripheral region surrounds the array region; a first gate layer surrounding the vertical transistor structure and extending along a first direction; a second gate layer surrounding the vertical transistor structure and extending along the first direction, where the second gate layer and the first gate layer surround a same vertical transistor structure, are disposed at intervals, and both extend to the peripheral region; and an electrical connection structure located in the peripheral region and electrically connected to the first gate layer and the second gate layer.