The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Jun. 25, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Chao Chou, Hsinchu, TW;

Yi-Hsun Chiu, Zhubei, TW;

Shang-Wen Chang, Jhubei, TW;

Ching-Wei Tsai, Hsinchu, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/50 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/50 (2013.01); H10D 30/62 (2025.01); H10D 62/118 (2025.01);
Abstract

Methods of forming dual-side super power rails in semiconductor devices, semiconductor devices including the same, and methods of testing the semiconductor devices are disclosed. In an embodiment, a device includes a transistor structure; a front-side interconnect structure on a front side of the transistor structure; and a back-side interconnect structure on a back side of the transistor structure. The front-side interconnect structure includes a front-side power delivery network (PDN) and a front-side input/output (I/O) pin. The back-side interconnect structure includes a back-side PDN.


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