The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Jan. 22, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Chuan Yang, Hsinchu, TW;

Jui-Wen Chang, Hsinchu, TW;

Feng-Ming Chang, Zhubei, TW;

Kian-Long Lim, Hsinchu, TW;

Kuo-Hsiu Hsu, Zhongli, TW;

Lien Jung Hung, Taipei, TW;

Ping-Wei Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 11/417 (2006.01); H10B 10/00 (2023.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); H10B 10/125 (2023.02); H10D 30/6735 (2025.01);
Abstract

The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.


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