Integrated circuit layouts with source and drain contacts of different widths

Abstract

A system for processing a layout of a semiconductor device includes a processor, and a computer readable storage medium. The processor is configured to execute instructions to generate an active region layout pattern extending in a first direction, generate a plurality of gate layout patterns extending in a second direction different from the first direction, wherein the plurality of gate layout patterns extends across the active region layout pattern, generate a plurality of source/drain region layout patterns in the active region layout pattern on opposite sides of the plurality of gate layout patterns, generate a plurality of source/drain contact layout patterns overlapping the plurality of source/drain region layout patterns, and generate one or more mark layers. Each of the mark layers labels a corresponding source/drain contact layout pattern of the plurality of source/drain contact layout patterns and is usable to indicate a width of the corresponding source/drain layout pattern.