The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jul. 25, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Hsin-Li Cheng, Hsinchu County, TW;

Yu-Chi Chang, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 62/83 (2025.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 62/83 (2025.01); H01L 21/76224 (2013.01); H10D 30/021 (2025.01); H10D 30/60 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 64/021 (2025.01);
Abstract

A method of manufacturing a semiconductor structure is disclosed. The method includes the following operations. An insulation region is formed in a substrate to define an active region in the substrate. A gate structure is formed across the active region. A source or drain region is formed in the active region and adjoins the insulation region. A resist protective dielectric film is formed, wherein the resist protective dielectric film overlaps an interface between the source or drain region and the insulation region, and exposes a portion of the source or drain region and a portion of the gate structure.


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