The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jun. 26, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Lin Lee, Hsinchu, TW;

Choh Fei Yeap, Hsinchu, TW;

Da-Wen Lin, Hsinchu, TW;

Chih-Chieh Yeh, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/00 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/764 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10D 30/031 (2025.01); H01L 21/0259 (2013.01); H01L 21/28123 (2013.01); H01L 21/764 (2013.01); H10D 30/6715 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/679 (2025.01);
Abstract

A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.


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