The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jul. 19, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Song-Fu Liao, Taipei, TW;

Kuo-Chang Chiang, Hsinchu, TW;

Hai-Ching Chen, Hsinchu, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 51/10 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H10B 51/10 (2023.02); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10D 64/689 (2025.01);
Abstract

In some embodiments, the present disclosure relates to a 3D memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.


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