The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Feb. 01, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Bo-Feng Young, Taipei, TW;

Sai-Hooi Yeong, Zhubei, TW;

Chih-Yu Chang, New Taipei, TW;

Han-Jong Chia, Hsinchu, TW;

Chenchen Jacob Wang, Hsinchu, TW;

Yu-Ming Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H10B 41/30 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 16/08 (2013.01); G11C 16/24 (2013.01); H10B 41/30 (2023.02); H10D 30/6735 (2025.01); H10D 62/119 (2025.01);
Abstract

A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.


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