The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Mar. 31, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tao Yi Hung, Hsinchu, TW;

Jam-Wem Lee, Hsinchu, TW;

Kuo-Ji Chen, Hsinchu, TW;

Wun-Jie Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H02H 1/00 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H02H 1/0007 (2013.01);
Abstract

Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.


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