The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jun. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Feng-Cheng Hsu, New Taipei, TW;

Shin-Puu Jeng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/6835 (2013.01); H01L 23/49811 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14517 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17517 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/94 (2013.01);
Abstract

A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.


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