The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2025
Filed:
Jul. 05, 2022
Applicant:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Inventors:
Assignee:
YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H10B 41/40 (2023.01); H10B 43/40 (2023.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/30604 (2013.01); H01L 21/31144 (2013.01); H01L 21/76859 (2013.01); H10B 41/40 (2023.02); H10B 43/40 (2023.02); H10D 84/0188 (2025.01); H10D 84/038 (2025.01);
Abstract
A semiconductor structure, fabrication method and three-dimensional memory are disclosed. A method of fabricating a semiconductor structure includes providing a substrate including a first device region and a second device region; forming a plurality of first recesses in the first device region and a second recess in the second device region, the first recesses and the second recess being formed simultaneously; forming a first isolation trench in the first device region; and forming a second isolation trench in the second device region at a position of the second recess.