The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

May. 19, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Min Gyu Sung, Latham, NY (US);

Julien Frougier, Albany, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Chanro Park, Clifton Park, NY (US);

Juntao Li, Cohoes, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4096 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 12/05 (2023.02); H10B 12/30 (2023.02); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01);
Abstract

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dynamic random-access-memory (DRAM), and the DRAM includes a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor, where a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via. A method of manufacturing the semiconductor structure is also provided.


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