The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Feb. 09, 2023
Applicant:

Intel Ndtm Us Llc, Santa Clara, CA (US);

Inventors:

Aliasgar S. Madraswala, Folsom, CA (US);

Shanmathi Mookiah, Santa Clara, CA (US);

Pratyush Chandrapati, Folsom, CA (US);

Naveen Prabhu Vittal Prabhu, Folsom, CA (US);

Assignee:

Intel NDTM US LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0608 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01);
Abstract

The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.


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