The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Apr. 15, 2021
Applicant:

Enkris Semiconductor, Inc., Jiangsu, CN;

Inventors:

Kai Cheng, Jiangsu, CN;

Liyang Zhang, Jiangsu, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10H 20/825 (2025.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01); H10H 20/01 (2025.01); H10H 20/817 (2025.01); H10H 20/857 (2025.01);
U.S. Cl.
CPC ...
H10H 20/825 (2025.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01); H10H 20/01335 (2025.01); H10H 20/817 (2025.01); H10H 20/857 (2025.01); H10H 20/0364 (2025.01);
Abstract

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure may include: a first epitaxial layer disposed on a substrate; a bonding layer disposed on the first epitaxial layer (where the bonding layer is provided with a first through-hole to expose the first epitaxial layer); a silicon substrate disposed on a side of the bonding layer away from the first epitaxial layer (where the first epitaxial layer is bonded to the silicon substrate by the bonding layer, the silicon substrate is provided with a through-silicon-via, and the through-silicon-via communicates with the first through-hole); a silicon device disposed on the silicon substrate; and a second epitaxial layer disposed on the first epitaxial layer exposed by the first through-hole. The present disclosure can improve the quality of the second epitaxial layer, and realize the integration of a silicon device and a III-V semiconductor device.


Find Patent Forward Citations

Loading…