Integrated circuits (ics) employing multi-pattern metallization to optimize metal interconnect spacing for improved performance and related fabrication methods

Abstract

An integrated circuit (IC) includes transistors formed in diffusion regions. In each transistor, a source and a drain extend in a first direction, and a gate is disposed on the diffusion region between the source and the drain. To reduce connection resistance through at least one of a source metal line and a drain metal line connected to the source and the drain of a transistor, one of the source metal line and the drain metal line extends farther than the other in the first direction to provide additional via landing area to support an interconnection via having reduced resistance without increasing side-to-side capacitance between the source and drain metal lines. Increasing the via landing area reduces connection resistance to the source and/or drain. Providing an extended source metal line and/or drain metal line allows a via landing area to be shifted in the first direction to reduce via capacitance.