The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

May. 12, 2022
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Naohiro Hosoda, Yokkaichi, JP;

Masanori Tsutsumi, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/10 (2023.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/53223 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a first metal oxide blocking dielectric layer, and a second metal oxide blocking dielectric layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the first metal oxide blocking dielectric layers and each of the electrically conductive layers.


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