The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Apr. 11, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Katherine Chiang, New Taipei, TW;

Chung Te Lin, Tainan, TW;

Min Cao, Hsinchu, TW;

Yuh-Jier Mii, Hsin-Chu, TW;

Sheng-Chih Lai, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
G11C 11/1659 (2013.01); G11C 11/161 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01);
Abstract

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an operative memory device. A regulating access apparatus is coupled to the operative memory device. The regulating access apparatus includes one or more regulating MTJ devices respectively having a regulating free layer, a regulating dielectric barrier layer, and a regulating pinned layer separated from the regulating free layer by the regulating dielectric barrier layer. The regulating pinned layer continuously extends between opposing outermost sidewalls of the regulating dielectric barrier layer.


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