The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Dec. 08, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Anthony St. Amour, Portland, OR (US);

Michael L. Hattendorf, Portland, OR (US);

Christopher P. Auth, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 10/00 (2023.01); H10D 1/47 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/0337 (2013.01); H01L 21/28247 (2013.01); H01L 21/28568 (2013.01); H01L 21/3086 (2013.01); H01L 21/31105 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/76816 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H10B 10/12 (2023.02); H10D 1/474 (2025.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6213 (2025.01); H10D 30/6219 (2025.01); H10D 30/792 (2025.01); H10D 30/795 (2025.01); H10D 62/151 (2025.01); H10D 64/015 (2025.01); H10D 64/689 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0177 (2025.01); H10D 84/0181 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01);
Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.


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