The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Dec. 17, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Chen Zhang, Guilderland, NY (US);

Jingyun Zhang, Albany, NY (US);

Carl Radens, LaGrangeville, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0128 (2025.01); H10D 84/014 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.


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