The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Jul. 13, 2023
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Masaaki Higashitani, Cupertino, CA (US);

Peter Rabkin, Cupertino, CA (US);

Hiroyuki Kinoshita, San Jose, CA (US);

Satoshi Shimizu, Yokkaichi, JP;

Yanli Zhang, San Jose, CA (US);

Johann Alsmeier, San Jose, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H10B 43/30 (2023.02);
Abstract

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.


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