The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Mar. 23, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wei-Ting Yeh, Hsinchu, TW;

Zheng Yong Liang, Hsinchu, TW;

De-Yang Chiou, Hsinchu, TW;

Yu-Yun Peng, Hsinchu, TW;

Keng-Chu Lin, Ping-Tung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); H01L 21/76251 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68372 (2013.01); H01L 2221/68386 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/83026 (2013.01); H01L 2224/83048 (2013.01); H01L 2224/83896 (2013.01); H01L 2924/0504 (2013.01); H01L 2924/0544 (2013.01); H01L 2924/059 (2013.01);
Abstract

The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.


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