The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Feb. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsu Ming Hsiao, Hsinchu, TW;

Hong Pin Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/28 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H01L 21/31116 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/667 (2025.01);
Abstract

Spacer layers on sidewalls of a dummy gate structure included in a semiconductor device are trimmed or etched prior to or during a replacement gate process in which the dummy gate structure is replaced with a replacement gate structure. A radical surface treatment operation is performed to etch the spacer layers, which is a type of plasma treatment in which radicals are generated using a plasma. The radicals in the plasma are used to etch the spacer layers such that the shape and/or the geometry of the remaining portions of the spacer layers reduces, minimizes, and/or prevents the likelihood of an antenna defect being formed in the spacer layers and/or in a work function metal layer of the replacement gate structure. This reduces, minimizes, and/or prevents the likelihood of occurrence of damage and/or defects in the replacement gate structure in subsequent processing operations for the semiconductor device.


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