The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

May. 24, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Michael A. Smith, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 64/00 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0227 (2025.01); H10D 30/601 (2025.01); H10D 64/112 (2025.01); H10D 64/512 (2025.01);
Abstract

An apparatus includes a substrate and a transistor disposed on the substrate. The transistor can include a gate disposed between a source area and a drain area of the transistor. The transistor can also include a plurality of routing lanes above the gate for use by automated routing programs that layout metal connections for the apparatus. A first field plate can be disposed above a LDD region of the source area with the first field plate being on a same level as the plurality of routing lanes. A second field plate can be disposed above a LDD region of the drain area with the second field plate being on the same level as the plurality of routing lanes. The first and second field plates can be electrically connected to the gate using respective first and second path that bypass the plurality of routing lanes.


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