The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Dec. 04, 2020
Applicant:

Tokyo Institute of Technology, Tokyo, JP;

Inventors:

Kuniyuki Kakushima, Tokyo, JP;

Hiroshi Funakubo, Tokyo, JP;

Shun-Ichiro Ohmi, Tokyo, JP;

Joel Molina Reyes, Tokyo, JP;

Ichiro Fujiwara, Tokyo, JP;

Atsushi Hori, Tokyo, JP;

Takao Shimizu, Tokyo, JP;

Yoshiko Nakamura, Tokyo, JP;

Takanori Mimura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 53/00 (2023.01); G11C 11/22 (2006.01); H10B 10/00 (2023.01); H10B 41/35 (2023.01); H10B 51/00 (2023.01);
U.S. Cl.
CPC ...
H10B 53/00 (2023.02); G11C 11/22 (2013.01); H10B 10/00 (2023.02); H10B 41/35 (2023.02); H10B 51/00 (2023.02);
Abstract

The invention provides a non-volatile storage element and non-volatile storage device employing a ferroelectric material with low power consumption, excellent high reliability, and especially write/erase endurance, which can be mixed with advanced CMOS logic. The non-volatile storage element has at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between both conductive layers, with a buffer layer having oxygen ion conductivity situated between the ferroelectric layer and the first conductive layer and/or second conductive layer. An interface layer composed of a single-layer film or a multilayer film may be also provided between the first conductive layer and the ferroelectric layer, the interface layer as a whole having higher dielectric constant than silicon oxide, and when the buffer layer is present between the first conductive layer and the ferroelectric layer, the interface layer is situated between the first conductive layer and the buffer layer. The non-volatile storage device comprises at least a memory cell array comprising low-power-consumption ferroelectric memory elements formed in a two-dimensional or three-dimensional configuration, and a control circuit. The ferroelectric layer is scalable to 10 nm or smaller and is fabricated at a low temperature of ≤400° C., and is subjected to low temperature thermal annealing treatment at ≤400° C. after the buffer layer has been formed, to provide high reliability.


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