The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Dec. 23, 2021
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Chaojun Deng, Dongguan, CN;

Xiaoyun Wei, Dongguan, CN;

Yong Yang, Xi'an, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/15 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 24/12 (2013.01); H01L 23/15 (2013.01); H01L 23/49822 (2013.01); H01L 23/49894 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 2224/81801 (2013.01);
Abstract

A chip package structure includes a glass substrate, a routing layer, and a plurality of dies. A first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls. The routing layer is located in the glass substrate, and the solder joints are electrically connected to the substrate solder balls by using the routing layer. Each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls. The embodiments can improve connection reliability between the die and the glass substrate and can reduce a signal transmission loss.


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