The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Apr. 19, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Ching Kang Chen, Kaohsiung, TW;

Kun-Ei Chen, Tainan County, TW;

Chen-Chieh Chiang, Kaohsiung, TW;

Ling-Sung Wang, Tainan, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 23/485 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76825 (2013.01); H01L 21/02112 (2013.01); H01L 21/30604 (2013.01); H01L 21/76813 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/485 (2013.01);
Abstract

A method for manufacturing a semiconductor structure is provided. The method may include several operations. A first layer is formed over a first region and a second region of a substrate. A first etching is performed on the first layer, thereby forming a first trench in the first region and a second trench in the second region. A first amorphization is performed on the first layer in the second region. A second etching is performed on the first layer, wherein an etching rate of the second etching in the second region is greater than an etching rate of the second etching in the first region.


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