The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Feb. 08, 2023
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Harold Pilo, Underhill, VT (US);

Shishir Kumar, Noida, IN;

Anurag Garg, Cupertino, CA (US);

Peter Lee, Pleasanton, CA (US);

John Edward Barth, Williston, VT (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/10 (2006.01); G11C 29/10 (2006.01);
U.S. Cl.
CPC ...
G11C 5/148 (2013.01); G11C 7/06 (2013.01); G11C 7/1096 (2013.01); G11C 7/222 (2013.01); G11C 8/10 (2013.01); G11C 29/10 (2013.01);
Abstract

A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.


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