The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Nov. 10, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Nicolas Loubet, Guilderland, NY (US);

Julien Frougier, Albany, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Prasad Bhosale, Albany, NY (US);

Junli Wang, Slingerlands, NY (US);

Balasubramanian Pranatharthiharan, Santa Clara, CA (US);

Dechao Guo, Niskayuna, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 88/00 (2025.01); H10D 30/67 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 88/00 (2025.01); H10D 30/6735 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 88/01 (2025.01);
Abstract

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.


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