The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Apr. 14, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yi Ting Liao, Changhua, TW;

Chao-Chi Chen, Tainan, TW;

Bo-Wei Chen, Kaohsiung, TW;

Shi Sheng Hu, Tainan, TW;

Shun Chi Tsai, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/00 (2025.01); H01L 21/28 (2006.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 64/118 (2025.01); H01L 21/28088 (2013.01); H10D 64/667 (2025.01); H10D 84/0177 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract

The present disclosure describes a semiconductor structure with a metal ion capture layer and a method for forming the structure. The method includes forming a first fin structure and a second fin structure on a substrate and forming a first gate structure over the first fin structure and a second gate structure over the second fin structure, where the first gate structure adjoins the second gate structure. The method further includes forming a dielectric layer on the first and second gate structures, removing a portion of the dielectric layer above an adjoining portion of the first and second gate structures to form an opening, and forming a metal ion capture layer in the opening.


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