The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Mar. 15, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Wei-Hsuan Chang, Tainan, TW;

Hao-Ping Yan, Tainan, TW;

Ming-Hua Tsai, Tainan, TW;

Chin-Chia Kuo, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H01L 21/266 (2006.01); H10D 30/60 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0227 (2025.01); H01L 21/266 (2013.01); H10D 30/601 (2025.01); H10D 62/102 (2025.01);
Abstract

A fabricating method of a middle voltage transistor includes providing a substrate. A gate predetermined region is defined on the substrate. Next, a mask layer is formed to cover only part of the gate predetermined region. Then, a first ion implantation process is performed to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions. After removing the mask layer, a gate is formed to overlap the entirety gate predetermined region. Subsequently, two second lightly doping regions respectively formed within one of the first lightly doping regions. Next, two source/drain doping regions are respectively formed within one of the second lightly doping regions. Finally, two silicide layers are formed to respectively cover one of the source/drain doping regions.


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