The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Apr. 18, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Semyeong Jang, Hefei, CN;

Joonsuk Moon, Hefei, CN;

Deyuan Xiao, Hefei, CN;

Jo-Lan Chin, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10B 12/05 (2023.02); H10B 12/315 (2023.02); H10D 30/031 (2025.01); H10D 30/6728 (2025.01);
Abstract

A semiconductor structure includes: a base including bit lines arranged at intervals and semiconductor channels arranged at intervals, bit lines extending in first direction, semiconductor channels being located at part of top surfaces of bit lines, each semiconductor channel including first area, second area, and third area arranged successively in a direction perpendicular to top surfaces of bit lines; dielectric layers located between adjacent bit lines and located on side walls of semiconductor channels; gate electrodes surrounding dielectric layers in second area and extending in second direction; metal semiconductor compound layers located on top surfaces of semiconductor channels; diffusion barrier layers at least surrounding side walls of metal semiconductor compound layers; and insulating layers located between adjacent semiconductor channels on same bit line and isolating gate electrodes and diffusion barrier layers on each dielectric layer from gate electrodes and diffusion barrier layers on dielectric layers adjacent to each dielectric layer.


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