The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2025
Filed:
Jan. 30, 2023
Kepler Computing Inc., San Francisco, CA (US);
Rajeev Kumar Dokania, Beaverton, OR (US);
Mustansir Yunus Mukadam, Seattle, WA (US);
Erik Unterborn, Cary, NC (US);
Pramod Kolar, Cary, NC (US);
Amrita Mathuriya, Portland, OR (US);
Debo Olaosebikan, San Francisco, CA (US);
Tanay Gosavi, Portland, OR (US);
Noriyuki Sato, Hillsboro, OR (US);
Sasikanth Manipatruni, Portland, OR (US);
Kepler Computing Inc., San Francisco, CA (US);
Abstract
Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.