The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2025
Filed:
Mar. 28, 2024
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
John Wiegert, Aloha, OR (US);
Joydeep Ray, Folsom, CA (US);
Timothy Bauer, Hillsboro, OR (US);
James Valerio, North Plains, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/355 (2018.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3887 (2013.01); G06F 9/355 (2013.01); G06F 9/3888 (2023.08); G06F 15/7839 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01);
Abstract
Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.