The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

May. 19, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hong-Shyang Wu, Taipei, TW;

Kuo-Ming Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8258 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/12 (2006.01); H10D 84/08 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10D 87/00 (2025.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H10D 84/08 (2025.01); H01L 23/535 (2013.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H10D 87/00 (2025.01); H01L 21/76251 (2013.01); H01L 21/76805 (2013.01); H01L 21/76898 (2013.01);
Abstract

In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.


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