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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12328922 B1

PDFFull Text
Date of Patent:
Jun. 10, 2025

Filed:

Feb. 27, 2024

Semiconductor device and method for fabricating the same

Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chih-Kai Hsu, Tainan, TW;

Ssu-I Fu, Kaohsiung, TW;

Yu-Hsiang Hung, Tainan, TW;

Wei-Chi Cheng, Kaohsiung, TW;

Jyh-Shyang Jenq, Pingtung County, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Attorney:

Winston Hsu

Primary Examiner:

Long Pham

Int. Cl.
CPC ...
H01L 29/08 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 62/151 (2025.01); H10D 30/024 (2025.01); H10D 30/60 (2025.01); H10D 30/601 (2025.01); H10D 30/62 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 64/017 (2025.01); H10D 64/512 (2025.01); H10D 64/516 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 30/0212 (2025.01);
Abstract

A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Find Patent Forward Citations

Hsu, Chih-Kai. (2025). Semiconductor device and method for fabricating the same (U.S. Patent No. 12328922). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12328922

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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