The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Dec. 21, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nicole K. Thomas, Portland, OR (US);

Payam Amin, Portland, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Hubert C. George, Portland, OR (US);

James S. Clarke, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 48/38 (2025.01); G06N 10/40 (2022.01); H03K 17/92 (2006.01); H10D 30/67 (2025.01); H10D 48/00 (2025.01); H10D 62/815 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 48/383 (2025.01); G06N 10/40 (2022.01); H03K 17/92 (2013.01); H10D 30/6733 (2025.01); H10D 62/8181 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01);
Abstract

Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.


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