3d 1t1c stacked dram structure and method to fabricate

Abstract

Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.