The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Dec. 21, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Wilfred Gomes, Portland, OR (US);

Abhishek Anil Sharma, Portland, OR (US);

Uygar Avci, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10B 53/30 (2023.01); H10B 53/40 (2023.01);
U.S. Cl.
CPC ...
G11C 11/2297 (2013.01); G11C 11/221 (2013.01); H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H10B 53/30 (2023.02); H10B 53/40 (2023.02);
Abstract

Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.


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