The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Oct. 16, 2020
Applicant:

Verity Ag, Zürich, CH;

Inventors:

Markus Hehn, Zürich, CH;

Fabio Rossetto, Zürich, CH;

Luciano Beffa, Zürich, CH;

Assignee:

Verity AG, Zürich, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/62 (2017.01); G06T 5/20 (2006.01); G06T 7/50 (2017.01); G06T 7/73 (2017.01); G06V 10/44 (2022.01); G06V 10/74 (2022.01); G06V 10/764 (2022.01);
U.S. Cl.
CPC ...
G06V 10/761 (2022.01); G06T 5/20 (2013.01); G06T 7/50 (2017.01); G06T 7/62 (2017.01); G06T 7/73 (2017.01); G06V 10/44 (2022.01); G06V 10/764 (2022.01);
Abstract

According to the present invention there is provide a method a method for matching features in an image with landmark representations in a landmark map, the method comprising: providing at least one image; extracting from the image one or more features; providing a landmark map comprising a list of landmark representations, wherein each landmark representation is a representation of a respective physical landmark; creating a plurality of policies, each policy comprising at least one matching decision of the feature and the landmark representation, each matching decision having a stage cost; assigning a policy cost to each of the policies, wherein the policy cost is a function of the stage costs of the matching decisions the policy is comprised of; selecting from the collection of the policies the policy with the desired policy cost. There is further provided an assembly having a processor which is configured to carry out said method.


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