The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Apr. 10, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ching-Hui Lin, Hsinchu, TW;

Chun-Ren Cheng, Hsinchu, TW;

Shih-Fen Huang, Jhubei, TW;

Fu-Chun Huang, Zhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N 27/414 (2006.01); B01L 3/00 (2006.01); G01N 27/30 (2006.01);
U.S. Cl.
CPC ...
G01N 27/4145 (2013.01); B01L 3/502715 (2013.01); G01N 27/302 (2013.01); G01N 27/4148 (2013.01);
Abstract

A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.


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