The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2025
Filed:
Sep. 03, 2024
Applicant:
Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);
Inventors:
Rajesh Katkar, Milpitas, CA (US);
Cyprian Emeka Uzoh, San Jose, CA (US);
Assignee:
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/68 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76843 (2013.01); H01L 21/68 (2013.01); H01L 23/53238 (2013.01); H01L 24/09 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08237 (2013.01); H01L 2225/06513 (2013.01); H01L 2924/37001 (2013.01);
Abstract
Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.