The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

May. 14, 2021
Applicant:

Intel Ndtm Us Llc, Santa Clara, CA (US);

Inventors:

Shantanu R. Rajwade, Santa Clara, CA (US);

Tarek Ahmed Ameen Beshari, Santa Clara, CA (US);

Matin Amani, Fremont, CA (US);

Narayanan Ramanan, San Jose, CA (US);

Arun Thathachary, Santa Clara, CA (US);

Assignee:

Intel NDTM US LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01);
Abstract

An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.


Find Patent Forward Citations

Rajwade, Shantanu. (2025). Program verify process having placement aware pre-program verify (ppv) bucket size modulation (U.S. Patent No. 12322455). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12322455

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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