The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Jan. 19, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Der Chih, Hsin-Chu, TW;

Chung-Cheng Chou, Hsin-Chu, TW;

Wen-Ting Chu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10B 63/84 (2023.02); H10N 70/253 (2023.02); H10N 70/841 (2023.02); G11C 13/0007 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/79 (2013.01); H10N 70/20 (2023.02); H10N 70/826 (2023.02); H10N 70/8833 (2023.02);
Abstract

A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.


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