The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2025
Filed:
Mar. 11, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Chieh Lee, Hsinchu, TW;
Chia-En Huang, Hsinchu County, TW;
Yi-Ching Liu, Hsinchu, TW;
Wen-Chang Cheng, Richmond, TX (US);
Yih Wang, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/4091 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 5/063 (2013.01); G11C 7/06 (2013.01); G11C 7/062 (2013.01); G11C 7/065 (2013.01); G11C 7/1078 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 7/1051 (2013.01); G11C 11/4093 (2013.01);
Abstract
A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.